1. Field of the Invention
The present invention relates to a top-gate type polycrystalline silicon thin film transistor (TFT).
2. Description of the Related Art
Polycrystalline silicon TFT's are used in integrated circuits, particularly, load elements of a static random access memory (SREM) and liquid crystal devices (LCD's).
In a prior art method for manufacturing a top-gate type TFT, a polycrystalline silicon layer, a gate insulating layer, a gate electrode layer, a non-doped insulating layer, and a metal connection layer are formed on a substrate, and then, a hydrogen passivation using hydrogenation by plasma discharge is carried out, to thereby reduce trap state densities of the polycrystalline silicon layer and improve the performance of the TFT. That is, a hydrogen passivation time is so long that saturated trap reduction characteristics and saturated threshold voltage characteristics can be obtained (see: I-WEI WU et al. "Effect of Trap-State Density Reduction by Plasma Hydrogeneration in Low-Temperature Polysilicon, TFT", IEEE ELECTRON DEVICE LETTERS, VOL. 10, No. 3, pp. 123-125, March 1989 and "Performance of Polysilicon TfT Digital Circuits Fabricated with Various Processing Techniques and Device Architechtures", SID 90 Digest, pp. 307-310, 1990). This will be explained later in detail.
In the above-described prior art method, when a gate length of the TFT is too small, for example, less than 10 .mu.m, a parasitic bipolar phenomenon may occur, so that the electric property is fluctuated. For example, the breakdown voltage of the TFT is reduced, and the threshold voltage of the TFT is fluctuated.